Mesh Routing Topologies For FPGA Arrays

There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce inter-chip routing costs by more than 50% over the basic 4-way Mesh. Introduction In the time since they were introduced, FPGAs have moved from being viewed simply as a method of implementing random logic in circuit boards to being a flexible implementation medium for many types of systems. Logic emulation tasks, in which ASIC designs are simulated on large FPGA-based structures [Butts92], have greatly increased simulation speeds. Software subroutines have been hand-optimized to FPGAs to speed up inner loops of programs [Bertin93], and work has been done to automate this process [Wazlowski93]. FPGA-based circuit implementation boards have been built for easier project construction in electronics education [Chan92, Chan93]. An important aspect shared by all of these systems is that they do not use single FPGAs, but harness multiple FPGAs, preconnected in a fixed routing structure, to perform their tasks. While FPGAs themselves can be routed and rerouted in their target systems, the pins moving signals between FPGAs are fixed by the routing structure on the implementation board. Field-Programmable Interconnects (FPICS)[Aptix93], chips that perform arbitrary routing between their pins, may remove some of the topology concerns from small arrays. However, large FPGA systems with FPICs for routing will still need to fix the topology for inter-FPIC routing. FPGA FPGA FPGA FPGA Logic Routing Routing Logic FPGA Logic & Routing FPGA Logic & Routing FPGA Logic & Routing FPGA Logic & Routing FPGA Logic FPGA Logic FPGA Routing FPGA Routing Figure 1. Some proposed FPGA routing structures. Mesh (left), Tree (center), Bipartite Graph (right). Several routing hierarchies have been used in recent FPGA-based systems. A Mesh structure, where the FPGAs are laid out in a two-dimensional grid, with an FPGA connected only to its four nearest neighbors, is employed in the PAM [Bertin93] software accelerator. A board being developed at MIT incorporates Mesh connections with routing similar to Superpins (described later in this paper)[Tessier93]. The Quickturn RPM [Butts92] logic emulator uses a hierarchy of partial crossbars, or Bipartite Graphs (However, the heirarchy is actually similar to a Tree, making the RPM a Tree of Bipartite Graphs). The BORG board [Chan92, Chan93], designed for use in electronics education, uses a Bipartite Graph where half the FPGAs are used for logic, and half for routing only. The routing structure used to interconnect individual chips in an FPGA array has a large impact not only on system speed, but also on required FPGA area, and system extendibility. A Bipartite Graph, with half of its FPGAs used for routing only, provides a predictable routing delay between logic FPGAs, since every inter-FPGA signal moves